DDR SDRAM
High-speed Double-Data-Rate Synchronous DRAMs which achieve great data speed by transferring data on both the rising and falling edges of the clock signal.
All ICs are RoHS compliant.
* Status: P - mass production, S - samples, UD - under development, N - not recommended for new design.
| Chip |
Description |
Density
(organization)
|
Clock
frequency
|
Supply
voltage
[V]
|
Operating
temperature
[°C]
|
Package
|
Status *
|
| Automotive |
Commercial
& Industrial |
W9464G6KH
 (1833 KB)
- density: 64 Mbit
- up to 200 MHz clock frequency
- speed grades: -5/-5I
- data bandwidth of up to 400 M words per second (DDR-500)
- differential clock inputs
- CAS Latency: 2, 2.5, 3
- burst length: 2, 4, 8
- Auto Refresh and Self Refresh
- Power-down Mode
- 4K refresh cycles / 64 ms
- interface: SSTL_2
- operating temperature range: commercial, industrial (I), automotive (A, K)
- compliance with AEC-Q100 automotive specification
|
64 Mbit
(4Mx16, 4 banks) |
200 MHz (-5/-5I)
DDR-400 |
2.5±0.2 |
0 – +70
-40 – +85 (I)
Automotive:
-40 – +85 (A)
-40 – +105 (K) |
TSOP(II)-66 |
P |
P | |
W9412G6JB
(864 KB)
- density: 128 Mbit
- up to 250 MHz clock frequency
- speed grades: -4/-5/-5I
- data bandwidth of up to 500 M words per second (DDR-500)
- differential clock inputs
- CAS Latency: 2, 2.5, 3
- burst length: 2, 4, 8
- Auto Refresh and Self Refresh
- Power-down Mode
- 4K refresh cycles / 64 ms
- interface: SSTL_2
- operating temperature range: commercial, industrial (I), automotive (A, K)
- compliance with AEC-Q100 automotive specification
|
128 Mbit
(8Mx16, 4 banks) |
250 MHz (-4)
DDR-500
200 MHz (-5/-5I)
DDR-400 |
2.4 – 2.7 (-4 speed grade)
2.5±0.2 (-5/-5I speed grades) |
0 – +70
-40 – +85 (I)
Automotive:
-40 – +85 (A)
-40 – +105 (K) |
TFBGA-60
8x13 mm |
P |
N | |
W9412G6KH
(1932 KB)
- density: 128 Mbit
- up to 200 MHz clock frequency
- speed grades: -5/-5I/-6I
- data bandwidth of up to 500 M words per second (DDR-500)
- differential clock inputs
- CAS Latency: 2, 2.5, 3
- burst length: 2, 4, 8
- Auto Refresh and Self Refresh
- Power-down Mode
- 4K refresh cycles / 64 ms
- interface: SSTL_2
- operating temperature range: commercial, industrial (I), automotive (A, K)
- compliance with AEC-Q100 automotive specification
|
128 Mbit
(8Mx16, 4 banks) |
250 MHz (-4)
DDR-500
200 MHz (-5/-5I)
DDR-400
166 MHz (-6I)
DDR-333 |
2.5±0.2 (-5/-5I/-6I speed grades) |
0 – +70
-40 – +85 (I)
Automotive:
-40 – +85 (A)
-40 – +105 (K) |
TSOP(II)-66 |
P |
P | |
W9425G6JB
(1914 KB)
- density: 256 Mbit
- up to 250 MHz clock frequency
- speed grade: -4/-5/-5I
- data bandwidth of up to 500 M words per second (DDR-400)
- differential clock inputs
- CAS Latency: 2, 2.5, 3
- burst length: 2, 4, 8
- Auto Refresh and Self Refresh
- Power-down Mode
- 8K refresh cycles / 64 ms
- interface: SSTL_2
- operating temperature range: commercial, industrial (I), automotive (A, K)
- compliance with AEC-Q100 automotive specification
|
256 Mbit
(16Mx16, 4 banks) |
250 MHz (-4)
DDR-500
200 MHz (-5/-5I)
DDR-400 |
2.4 – 2.7 (-4 speed grade)
2.5±0.2 (-5/-5I speed grades) |
0 – +70
-40 – +85 (I)
Automotive:
-40 – +85 (A)
-40 – +105 (K) |
TFBGA-60 |
P |
N | |
W9425G6KH
(1850 KB)
- density: 256 Mbit
- up to 250 MHz clock frequency
- speed grades: -4/-5/-5I
- data bandwidth of up to 500 M words per second (DDR-500)
- differential clock inputs
- CAS Latency: 2, 2.5, 3
- burst length: 2, 4, 8
- Auto Refresh and Self Refresh
- Power-down Mode
- 8K refresh cycles / 64 ms
- interface: SSTL_2
- operating temperature range: commercial, industrial (I), automotive (A, K)
- compliance with AEC-Q100 automotive specification
|
256 Mbit
(16Mx16, 4 banks) |
250 MHz (-4)
DDR-500
200 MHz (-5/-5I)
DDR-400 |
2.4 – 2.7 (-4 speed grade)
2.5±0.2 (-5/-5I speed grades) |
0 – +70
-40 – +85 (I)
Automotive:
-40 – +85 (A)
-40 – +105 (K) |
TSOP(II)-66 |
P |
P | |
|
