PDW MARTHEL

Synchronization modules

Synchronization modules for STRATUM

Part type	Description	Frequency range [MHz]	Frequency stability	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]
Part type	Description	Frequency range [MHz]	Frequency stability	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]
SY01−S3 (165 kB)	A synchronization module based on OCXO, designed for STRATUM 3 applications in ATM, PDH, SDH and SONET systems: digital PLL two reference inputs from two independent souces in the range from 8 kHz to 77.76 MHz two frequency outputs up to 77.76 MHz four timing modes: free-run, locked to reference 1, locked to reference 2, holdover host interface and JTAG port	8 kHz ~ 77.76	±0.28 PPM ±1 PPM	HCMOS	5.0	-20 ~ +70	50.1 x 50.1 x 19.5 (DIP-18)
SY01−S3T (173 kB)	A synchronization module based on TCXO, designed for STRATUM 3 applications in ATM, PDH, SDH and SONET systems: digital PLL two reference inputs from two independent souces in the range from 8 kHz to 77.76 MHz two frequency outputs up to 77.76 MHz four timing modes: free-run, locked to reference 1, locked to reference 2, holdover host interface and JTAG port	8 kHz ~ 77.76	±0.28 PPM ±1 PPM	HCMOS	5.0	-20 ~ +70	50.1 x 50.1 x 19.5 (DIP-18)
SY01−SMC (144 kB)	A synchronization module based on VCXO, designed for SONET/SDH systems in accordance with specification for SONET Minimum Clock (SMC): digital PLL two reference inputs from two independent souces in the range from 8 kHz to 77.76 MHz two frequency outputs up to 77.76 MHz four timing modes: free-run, locked to reference 1, locked to reference 2, holdover host interface and JTAG port	8 kHz ~ 77.76	±4.1 PPM	HCMOS	5.0	-20 ~ +70	45.7 x 45.7 x 14.0 (DIP-18)
SY01−S3F (164 kB)	A synchronization module based on OCXO, designed for STRATUM 3 applications in ATM, PDH, SDH and SONET systems: digital PLL two reference inputs from two independent souces in the range from 8 kHz to 77.76 MHz two frequency outputs up to 77.76 MHz four timing modes: free-run, locked to reference 1, locked to reference 2, holdover an additional TCXO free-run output within ±4.6 PPM host interface and JTAG port	8 kHz ~ 77.76	±0.28 PPM ±1 PPM	LVCMOS/HCMOS	5.0	-20 ~ +70	50.1 x 50.1 x 19.5 (DIP-18)

PLL synchronizers

Part type	Description	Frequency range [MHz]	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]
Part type	Description	Frequency range [MHz]	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]
SY02−PLL (261 kB)	Low frequency PLL synchronizer based on VCXO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL reference input with four selectable frequencies: 8 / 16 / 32 / 64 kHz tri-state oscillator output up to 77.76 MHz an additional free-run clock output within ±20 PPM JTAG port	8 kHz ~ 77.76	HCMOS with enable/disable function	3.3	0 ~ +70	SMD 14-pin J-leads 14-pin (see documentation)
SY02−PLL2 (150 kB)	Dual input low frequency PLL synchronizer based on VCXO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz tri-state oscillator output up to 77.76 MHz an additional free-run clock output within ±20 PPM JTAG port	8 kHz ~ 77.76	LVHCMOS with enable/disable function	3.3	0 ~ +70	19.0 x 20.6 x 4.1 (SMD 14-pin)
SY02−HPLL (338 kB)	High frequency PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz tri-state differential output up to 777.6 MHz an additional free-run clock output within ±32 PPM JTAG port	51.84 ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70	SMD 14-pin J-leads 14-pin (see documentation)
SY02−HIPL (311 kB)	High frequency PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL one reference input in the range from 19.44 MHz to 777.6 MHz one tri-state differential output up to 777.6 MHz an additional free-run clock output within ±30 PPM (VCXO) or ±150 PPM (VCSO) JTAG port	19.44 ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70	26.4 x 26.7 x 10.6 (J-leads 18-pin)
SY02−HP20 (311 kB)	Dual output high frequency PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL one reference input in the range from 8 kHz to 77.76 MHz two pairs of high frequency differential outputs up to 666.5 MHz JTAG port	51.84 ~ 666.5143	LVPECL	3.3	0 ~ +70	20.3 x 24.1 x 9.6 (SMD 20-pin)
SY02−HLPL (253 kB)	Dual input high frequency hitless switching PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz tri-state differential output up to 666.5 MHz an additional free-run clock output within ±30 PPM (VCXO) or ±150 PPM (VCSO) JTAG port	51.84 ~ 666.513	LVPECL with enable/disable function	3.3	0 ~ +70	26.4 x 22.0 x 10.6 (J-leads 18-pin)
SY02−FEC (290 kB)	High frequency clock regenerator based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET, DWDM, FEC and other telecommunication systems: digital PLL two reference inputs in the range from 77.76 MHz to 777.6 MHz one tri-state differential output up to 777.6 MHz JTAG port	77.76 ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70	25.4 x 20.3 x 6.4 (SMD 16-pin)
SY02−MFTC (98 kB)	Low frequency clock regenerator based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET, DWDM, FEC and other telecommunication systems: digital PLL one reference input in the range from 8 kHz to 77.76 MHz one tri-state output up to 77.76 MHz JTAG port	8 kHz ~ 77.76	HCMOS/LVCMOS with enable/disable function	3.3	0 ~ +70 -40 ~ +85	25.4 x 20.3 x 6.4 (SMD 16-pin)
SY02−MFTP (97 kB)	High frequency clock regenerator based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET, DWDM, FEC and other telecommunication systems: digital PLL one reference input in the range from 8 kHz to 77.76 MHz one tri-state output up to 777.6 MHz JTAG port	8 kHz ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70 -40 ~ +85	25.4 x 20.3 x 6.4 (SMD 16-pin)

Hitless schwitching synchronization modules

Part type	Description	Frequency range [MHz]	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]

SY05−HLPL (149 kB)	Dual input/output high frequency hitless switching PLL synchronizer based on VCXO, designed for ATM, PDH, SDH and SONET systems: digital PLL hitless switching between two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz two LVPECL differential outputs: the main output up to 777.6 MHz, secondary output at main frequency divided by 2,4 or 8 four timing modes: free-run, locked to reference 1, locked to reference 2, loop-back timing	1.024 ~ 777.6	LVPECL	3.3	-20 ~ +70	50.0 x 50.0 x 8.3 (DIP 28-pin)
SY05−HF (187 kB)	Multi output high frequency hitless switching PLL synchronizer based on VCXO, designed for ATM, PDH, SDH and SONET systems: digital PLL hitless switching between two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz up to four LVPECL differential outputs and two LVCMOS outputs up to 777.6 MHz four timing modes: free-run, locked to reference 1, locked to reference 2, loop-back timing	51.84 ~ 777.6	LVPECL LVCMOS	3.3	-40 ~ +85	46.2 x 46.2 x 13.2 (DIP 34-pin)

Synchronization modules for STRATUM 3/3E

Part type	Description	Frequency range [MHz]	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]

SY10 (268 kB)	Multi output synchronizer based on OCXO, designed for STRATUM 3 and 3E applications in ATM, PDH, SDH and SONET systems: digital PLL six reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz three outputs up to 77.76 MHz three timing modes: free-run, locked, holdover host interface SPI and JTAG port	8 kHz ~ 77.76	HCMOS	3.3	-20 ~ +70	46.2 x 46.2 x 16.0 (DIP 34-pin)

HF synchronization modules for STRATUM 3

Part type	Description	Frequency range [MHz]	Output level	Supply voltage [V]	Operating temperature [°C]	Dimensions [mm]

SY15 (170 kB)	Multi output high frequency synchronizer based on OCXO or TCXO, designed for STRATUM 3 applications in ATM, PDH, SDH and SONET systems: digital PLL five reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz three differential outputs up to 622.08 MHz three timing modes: free-run, locked, holdover host interface SPI and JTAG port	155.52 ~ 622.08	PECL with enable/disable function	5 or 3.3 (PECL)	-20 ~ +70	46.2 x 46.2 x 16.0 (DIP 34-pin)