Synchronization modules

PLL synchronizers

Part type	Description	Frequency  range [MHz]	Output level	Supply   voltage   [V]	Operating temperature [°C]	Dimensions  [mm]
SY02-PLL  (261 kB)	Low frequency PLL synchronizer based on VCXO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL reference input with four selectable frequencies: 8 / 16 / 32 / 64 kHz tri-state oscillator output up to 77.76 MHz an additional free-run clock output within ±20 PPM JTAG port	8 kHz ~ 77.76	HCMOS with enable/disable function	3.3	0 ~ +70	SMD 14-pin J-leads 14-pin (see documentation)
SY02-PLL2  (150 kB)	Dual input low frequency PLL synchronizer based on VCXO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz tri-state oscillator output up to 77.76 MHz an additional free-run clock output within ±20 PPM JTAG port	8 kHz ~ 77.76	LVHCMOS with enable/disable function	3.3	0 ~ +70	19.0 x 20.6 x 4.1 (SMD 14-pin)
SY02-HPLL  (338 kB)	High frequency PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz tri-state differential output up to 777.6 MHz an additional free-run clock output within ±32 PPM JTAG port	51.84 ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70	SMD 14-pin J-leads 14-pin (see documentation)
SY02-HIPL  (311 kB)	High frequency PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL one reference input in the range from 19.44 MHz to 777.6 MHz one tri-state differential output up to 777.6 MHz an additional free-run clock output within ±30 PPM (VCXO) or ±150 PPM (VCSO) JTAG port	19.44 ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70	26.4 x 26.7 x 10.6 (J-leads 18-pin)
SY02-HP20  (311 kB)	Dual output high frequency PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL one reference input in the range from 8 kHz to 77.76 MHz two pairs of high frequency differential outputs up to 666.5 MHz JTAG port	51.84 ~ 666.5143	LVPECL	3.3	0 ~ +70	20.3 x 24.1 x 9.6 (SMD 20-pin)
SY02-HLPL  (253 kB)	Dual input high frequency hitless switching PLL synchronizer based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET and other telecommunication systems: digital PLL two reference inputs with selectable frequencies in the range from 8 kHz to 77.76 MHz tri-state differential output up to 666.5 MHz an additional free-run clock output within ±30 PPM (VCXO) or ±150 PPM (VCSO) JTAG port	51.84 ~ 666.513	LVPECL with enable/disable function	3.3	0 ~ +70	26.4 x 22.0 x 10.6 (J-leads 18-pin)
SY02-FEC  (290 kB)	High frequency clock regenerator based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET, DWDM, FEC and other telecommunication systems: digital PLL two reference inputs in the range from 77.76 MHz to 777.6 MHz one tri-state differential output up to 777.6 MHz JTAG port	77.76 ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70	25.4 x 20.3 x 6.4 (SMD 16-pin)
SY02-MFTC  (98 kB)	Low frequency clock regenerator based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET, DWDM, FEC and other telecommunication systems: digital PLL one reference input in the range from 8 kHz to 77.76 MHz one tri-state output up to 77.76 MHz JTAG port	8 kHz ~ 77.76	HCMOS/LVCMOS with enable/disable function	3.3	0 ~ +70 -40 ~ +85	25.4 x 20.3 x 6.4 (SMD 16-pin)
SY02-MFTP  (97 kB)	High frequency clock regenerator based on VCXO or VCSO, designed for ATM, PDH, SDH, SONET, DWDM, FEC and other telecommunication systems: digital PLL one reference input in the range from 8 kHz to 77.76 MHz one tri-state output up to 777.6 MHz JTAG port	8 kHz ~ 777.6	LVPECL with enable/disable function	3.3	0 ~ +70 -40 ~ +85	25.4 x 20.3 x 6.4 (SMD 16-pin)