Audio CODECs

Stereo ADC


All ICs are RoHS compliant.

* Status: P - mass production, S - samples, UD - under development, N - not recommended for new design.

Chip Description Supply
  voltage  
[V]		 Sampling
frequency
 (bandwidth) 		 Operating
temperature
[°C]		    Package    Status *
NAU8501
 (2113 kB) 		Stereo ADC:
  • 24-bit signal processing
  • SNR ≥ 90 dB and THD ≤ -80 dB
  • notch filter and programmable high pass filter
  • automatic level control (ALC) with audio level limiter
  • programmable PLL
  • stereo line input
  • stereo differential microphone amplifier
  • input mixer for analog signals
  • stereo line output
  • I2S and µ-Law/A-Law PCM audio interfaces
  • 2/3/4-wire control interface (I2C or SPI)
  • 5-band equalizer
  • 3-D stereo enhancement
 Analog: 2.5 – 3.6
Digital: 1.65 – 3.6		 8 - 48 kHz   QFN-32 P
NAU8502
 (3313 kB) 		Stereo ADC:
  • 24-bit signal processing
  • SNR ≥ 90 dB and THD ≤ -80 dB
  • notch filter and programmable high pass filter
  • automatic level control (ALC) with audio level limiter
  • programmable PLL
  • stereo line input
  • stereo differential microphone amplifier
  • input mixer for analog signals
  • stereo line output
  • I2S and µ-Law/A-Law PCM audio interfaces
  • 2/3/4-wire control interface (I2C or SPI)
  • 5-band equalizer
  • 3-D stereo enhancement
  • integrated LDO
 Analog: 2.5 – 3.6
Digital: 1.65 – 3.6		 8 - 48 kHz -40 – +85 QFN-32 P
NAU85L40
 (2017 kB) 		Quad ultra low power ADC:
  • 24-bit signal processing
  • SNR ≥ 101 dB and THD ≤ -90 dB
  • notch filter and programmable high pass filter
  • automatic level control (ALC) with audio level limiter
  • programmable FLL (Frequency Locked Loop)
  • four differential microphone amplifiers
  • I2S and µ-Law/A-Law PCM audio interfaces
  • I2C control interface
 Analog: 1.62 – 1.98
Digital: 1.2 – 1.98		 8 - 48 kHz -40 – +85 QFN-28 P